<?xml version="1.0" encoding="UTF-8"?><rss version="2.0"
	xmlns:content="http://purl.org/rss/1.0/modules/content/"
	xmlns:wfw="http://wellformedweb.org/CommentAPI/"
	xmlns:dc="http://purl.org/dc/elements/1.1/"
	xmlns:atom="http://www.w3.org/2005/Atom"
	xmlns:sy="http://purl.org/rss/1.0/modules/syndication/"
	xmlns:slash="http://purl.org/rss/1.0/modules/slash/"
	>

<channel>
	<title>Spartan-3 | TechLiebe</title>
	<atom:link href="https://techliebe.com/tag/spartan-3/feed/" rel="self" type="application/rss+xml" />
	<link>https://techliebe.com</link>
	<description>The World of Ubiquitous Technology.</description>
	<lastBuildDate>Sun, 15 Mar 2026 19:42:40 +0000</lastBuildDate>
	<language>en-US</language>
	<sy:updatePeriod>
	hourly	</sy:updatePeriod>
	<sy:updateFrequency>
	1	</sy:updateFrequency>
	<generator>https://wordpress.org/?v=6.9.4</generator>

<image>
	<url>https://techliebe.com/wp-content/uploads/2016/06/Fevicon_techliebe_50x50.jpg</url>
	<title>Spartan-3 | TechLiebe</title>
	<link>https://techliebe.com</link>
	<width>32</width>
	<height>32</height>
</image> 
	<item>
		<title>32 bit Floating point addition using FPGA PART-II</title>
		<link>https://techliebe.com/32-bit-floating-point-addition-using-fpga-part-ii-2/</link>
					<comments>https://techliebe.com/32-bit-floating-point-addition-using-fpga-part-ii-2/#respond</comments>
		
		<dc:creator><![CDATA[nikhil kalsekar]]></dc:creator>
		<pubDate>Wed, 23 Jul 2014 20:10:57 +0000</pubDate>
				<category><![CDATA[TechLogic]]></category>
		<category><![CDATA[Technology]]></category>
		<category><![CDATA[32Bit Addition]]></category>
		<category><![CDATA[Electronics]]></category>
		<category><![CDATA[Floating point]]></category>
		<category><![CDATA[IEEE 754]]></category>
		<category><![CDATA[Modelsim]]></category>
		<category><![CDATA[Spartan-3]]></category>
		<category><![CDATA[Testbench]]></category>
		<category><![CDATA[VLSI]]></category>
		<category><![CDATA[Xilinx]]></category>
		<guid isPermaLink="false">http://techliebe.com/?p=1003</guid>

					<description><![CDATA[<p>In Previous Article i.e.&#160;FPGA Part -I, we have seen Floating Point Addition. Let&#8217;s start with the representation of floating point numbers in this article. &#160; ii. Representation of floating point numbers &#160; Floating Point Numbers The term floating point is derived from the fact that there is no fixed number of digits before and after [&#8230;]</p>
The post <a href="https://techliebe.com/32-bit-floating-point-addition-using-fpga-part-ii-2/">32 bit Floating point addition using FPGA PART-II</a> first appeared on <a href="https://techliebe.com">TechLiebe</a>.]]></description>
		
					<wfw:commentRss>https://techliebe.com/32-bit-floating-point-addition-using-fpga-part-ii-2/feed/</wfw:commentRss>
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			</item>
		<item>
		<title>32 bit Floating point addition using FPGA (PART-I)</title>
		<link>https://techliebe.com/32-bit-floating-point-addition-using-fpga-part-i/</link>
					<comments>https://techliebe.com/32-bit-floating-point-addition-using-fpga-part-i/#respond</comments>
		
		<dc:creator><![CDATA[nikhil kalsekar]]></dc:creator>
		<pubDate>Mon, 14 Jul 2014 19:27:11 +0000</pubDate>
				<category><![CDATA[Technology]]></category>
		<category><![CDATA[32Bit]]></category>
		<category><![CDATA[Addition]]></category>
		<category><![CDATA[Electronics]]></category>
		<category><![CDATA[Floating point]]></category>
		<category><![CDATA[IEEE 754]]></category>
		<category><![CDATA[Modelsim]]></category>
		<category><![CDATA[Spartan-3]]></category>
		<category><![CDATA[Testbench]]></category>
		<category><![CDATA[VLSI]]></category>
		<category><![CDATA[Xilinx]]></category>
		<guid isPermaLink="false">http://techliebe.com/?p=977</guid>

					<description><![CDATA[<p>&#160; This article is base on a project executed on the Spartan-3 kit. Let&#8217;s get on with what exactly the article will consist of: Arithmetic circuits form an important class of circuits in digital systems. Tremendous progress in the very large scale integration (VLSI) circuit technology has led to simplify, many complex circuits. Algorithms that [&#8230;]</p>
The post <a href="https://techliebe.com/32-bit-floating-point-addition-using-fpga-part-i/">32 bit Floating point addition using FPGA (PART-I)</a> first appeared on <a href="https://techliebe.com">TechLiebe</a>.]]></description>
		
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			</item>
	</channel>
</rss>
